Remote-processing RPC-220 Instrukcja Użytkownika Pobierz pdf (Strona 32)

WATCHDOG TIMER SECTION 9

Page 9-1

Figure 9-1 Watchdog Jumper Location

WATCHDOG TIMER SECTION 9

A watch dog timer resets the CPU if it enters erroneous

processor states or "loop fo rever " code . T he timer is

reloaded in periods that are shorter than the watchdog

interval. The timer is built into the CPU and is enabled

or disabled by jumper W6.

OPERATION

When the watchdog timer is enabled and overflow s, a

short reset pulse, internal to the CPU, is generated. A

short output pulse is also generated but does not have

any effect on the reset signal at J2 or J3.

Inform ation about the w atchdog star ts on page 3-48 0 in

the 8X0C552OV.PDF file.

The timer consists of an 8 bit timer and an 11 bit

prescaler. The 8 bit timer is loaded to prevent a reset

pulse. Watchdog timer interval is determined by the

following formula:

interval = 1.111 ms * timer_value

The watchdog ser vice routine is very short:

watchdog:

ORL PCON,#10H ;set condition

MOV T3,timer_value ;load with

;interval

RET

This should be in assembly language even when using C

to prevent it from wrongly manipulating PCON. The

address of T3 is 0xff.

USE DURING DEVELOPMENT

The watchdog jumper W 6 is set to [1-2] to disable it. If

you want to enable it for debugging purposes, you can

set the jumper to enable (W6[2-3]) while your program

is running. If a watchdog crash happens, the program

will reset and the monitor program

When your program is in flash, you can set W 6[2-3] all

of the time.

On power up or reset, the watchdog timer is reset to 0,

which is a timeout interval of 283 ms. This is enough

time for basic system initialization (memory and I/O

states). If you are perform ing extensive initialization

(such as clearing 512K of RAM) then you should put the

watchdog routine as part of the program.

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